1. FIELD OF THE INVENTION
This invention relates to a semiconductor package, and in particular, to the structure of a package into which dielectric substrates with peripheral circuits formed by patterning are package together with semiconductor chips.
2. DESCRIPTION OF THE RELATED ART
FIGS. 5A and 5B show the structure of a conventional semiconductor device. It includes a package base 1 which is made of Cu and which has a rectangular protrusion 1a in its center. Formed on this protrusion 1a is a chip mounting section 1b in the form of a ridge extending along a line which is not always located on the central line of the package base 1. A semiconductor chip 8 is soldered to this chip mounting section 1b, and substrate cracking prevention plates 5 are soldered onto the upper surfaces of the protrusion 1a. A dielectric substrate 6 is soldered onto each of these substrate cracking prevention plates 5. The substrate cracking prevention plates 5 prevent any stress caused by the difference in the thermal expansion coefficients of the package base 1 and the dielectric substrates 6 from concentrating on the dielectric substrates 6. Accordingly, the plates 5 have a coefficient of thermal expansion lying between that of the package base 1 and that of the dielectric substrates 6. Peripheral circuits 6a such as matching circuits or bias circuits are formed by patterns of metal disposed on the dielectric substrates 6, the electrodes of the semiconductor chip 8 being connected to the respective peripheral circuits 6a through connecting wires 9 made of gold or the like. Further, the peripheral circuits 6a are connected to outwardly extending leads 7 through respective connecting wires 9.
An annular package frame 2 is brazed to the upper surface of the package base 1 so that it surrounds the protrusion 1a except for those sections where the external leads 7 are located. The leads 7 are mounted on ceramic bases 3 which are brazed onto the base 1. Brazed onto these ceramic bases 3 are ceramic tops 4, onto which the above-mentioned package frame 2 is brazed.
A cap 10 is soldered to the top section of the package frame 2. The cap 10, the package base 1, the package frame 2 and other elements define a cavity A for sealing the semiconductor chip 8, the dielectric substrates 6 and the substrate cracking prevention plates 5.
Thus, in the above-described semiconductor package, the chip mounting section 1b is formed on the package base 1, the semiconductor chip 8 being mounted on this chip mounting section 1b. Accordingly, the positions of the semiconductor chip 8 and of the dielectric substrates 6 are determined by the package base 1. That is, different package bases 1 may have to be used for different semiconductor chips 8 for different applications, resulting in poor utility.
In addition, the complicated configuration of the package base 1 requires close dimensional tolerances, resulting in a high production cost for manufacturing the semiconductor package.